Architect Labs says it can design an inference chip in less than two weeks, from specification to FPGA

The start-up claims that an AI system can design an inference chip on its own, with 95% code coverage without a verification engineer. Silicon, on the other hand, remains to be engraved.

Inference chips are usually frozen for several years before the models they will have to run are running. Architect Labs claims to have reduced this cycle to less than two weeks between specification and a functional implementation on FPGA, and to less than forty-eight hours for a change. One figure serves as a benchmark for the scale of the targeted problem: in 2024, only 14% of integrated circuit projects were running from the first silicon.

The company claims 95% code coverage achieved without a human verification engineer, and optimization phases reduced from fifteen hours to half an hour on FPGAs. Its first design, called Redwood Nano, is estimated at 49 tokens per second for 1.335 watts, compared to 2.59 watts for Nvidia's Jetson Orin Nano reference — projections, not measurements on an engraved chip.

This is the main limitation of the announcement: only the implementation on FPGAs has been demonstrated, with manufacturing at TSMC still to come. The company defends a broader thesis than the simple gain in productivity, summarized as follows: AI applied to hardware design would not consist of accelerating tasks in existing flows, but of rethinking the flow itself.