Eleven 5.7 GHz cores capable of switching between instruction sets in nanoseconds, with built-in inference accelerators and a preview of the next-generation Spyre AI chip.
On August 24, 2026, IBM detailed the successor to the processor that powers its mainframes, presented as the first mainframe chip capable of natively running the Z instruction set and the Arm instruction set on the same cores. Each of the eleven cores can switch from one software mode to the other in a matter of nanoseconds.
The chip is engraved in 2 nanometers, its cores run at 5.7 GHz base frequency, and it has inference accelerators dedicated to fraud detection, as well as a data processing unit dedicated to I/O. Complete systems must scale up to several hundred cores and tens of terabytes of memory.
IBM is taking advantage of the announcement to give a preview of the next generation of its Spyre accelerator, equipped with high-bandwidth memory and intended to run large language models in agentic processing chains — document understanding, insurance case instruction. Christian Jacobi, IBM Fellow, justifies this choice of deep integration by the need to offer AI the same service guarantees as the rest of the machine. Commercialization is expected around 2028, in line with the three-year cycle of the range, with the z17 having been delivered in the second quarter of 2025.
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